ARTICo³ Publications

Cite ARTICo³

Please, use the following reference if you use ARTICo³ in your scientific paper or if you want to cite it:

Rodríguez, A.; Valverde, J.; Portilla, J.; Otero, A.; Riesgo, T.; de la Torre, E. FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo³ Framework. Sensors 2018, 18, 1877.

@Article{rodriguez18_artico3,
    AUTHOR = {Rodr\'iguez, Alfonso and Valverde, Juan and Portilla, Jorge and Otero, Andr\'es and Riesgo, Teresa and de la Torre, Eduardo},
    TITLE = {{FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo\textsuperscript{3} Framework}},
    JOURNAL = {Sensors},
    VOLUME = {18},
    YEAR = {2018},
    NUMBER = {6},
    ARTICLE-NUMBER = {1877},
    URL = {https://www.mdpi.com/1424-8220/18/6/1877},
    ISSN = {1424-8220},
    DOI = {10.3390/s18061877}
}

Publications

Journal Publications

2020

• Barrios, Y.; Rodríguez, A.; Sánchez, A.; Pérez, A.; López, S.; Otero, A.; de la Torre, E.; Sarmiento, R. Lossy Hyperspectral Image Compression on a Reconfigurable and Fault-Tolerant FPGA-Based Adaptive Computing Platform. Electronics 2020, 9, 1576.

• L. Suriano, A. Otero, A. Rodríguez, M. Sánchez-Renedo and E. de la Torre, “Exploiting Multi-Level Parallelism for Run-Time Adaptive Inverse Kinematics on Heterogeneous MPSoCs,” in IEEE Access, vol. 8, pp. 118707-118724, 2020.

• A. Pérez, A. Rodríguez, A. Otero, D. G. Arjona, Á. Jiménez-Peralo, M. Á. Verdugo and E. de la Torre, “Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation,” in IEEE Access, vol. 8, pp. 59891-59905, 2020.

2019

• A. Rodríguez, L. Santos, R. Sarmiento and E. de la Torre, “Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression,” in IEEE Access, vol. 7, pp. 10644-10652, 2019.

2018

• Ortiz, A.; Rodríguez, A.; Guerra, R.; López, S.; Otero, A.; Sarmiento, R.; de la Torre, E. A Runtime-Scalable and Hardware-Accelerated Approach to On-Board Linear Unmixing of Hyperspectral Images. Remote Sens. 2018, 10, 1790.

• Rodríguez, A.; Valverde, J.; Portilla, J.; Otero, A.; Riesgo, T.; de la Torre, E. FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo³ Framework. Sensors 2018, 18, 1877.

Conference Publications

2020

• A. Ortiz, R. Zamacola, A. Rodríguez, A. Otero, E. de la Torre, “Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems”, in F. Rincón, J. Barba, H. K. H. So, P. Diniz, J. Caba, editors, Applied Reconfigurable Computing. Architectures, Tools, and Applications, pp. 45–60, Springer International Publishing, Cham, 2020.

2019

• A. Ortiz, A. Rodríguez, A. Otero and E. de la Torre, “Data Transfer Modeling and Optimization in Reconfigurable Multi-Accelerator Systems,” 2019 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), York, United Kingdom, 2019, pp. 20-26.

2018

• A. Rodríguez and T. Fanni, “DEMO: Multi-Grain Adaptivity in Cyber-Physical Systems,” 2018 30th International Conference on Microelectronics (ICM), Sousse, Tunisia, 2018, pp. 44-47.

• T. Fanni et al., “Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems,” 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico, 2018, pp. 1-8.

• L. Suriano, D. Madroñal, A. Rodríguez, E. Juárez, C. Sanz and E. de la Torre, “A Unified Hardware/Software Monitoring Method for Reconfigurable Computing Architectures Using PAPI,” 2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Lille, 2018, pp. 1-8.

2015

• A. Rodríguez, J. Valverde and E. de la Torre, “Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs,” 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Mexico City, 2015, pp. 1-7.

• A. Rodríguez, J. Valverde, C. Castañares, J. Portilla, E. de la Torre and T. Riesgo, “Execution modeling in self-aware FPGA-based architectures for efficient resource management,” 2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Bremen, 2015, pp. 1-8.

• A. Rodríguez, J. Valverde, C. Castañares, J. Portilla, E. de la Torre and T. Riesgo, “Live demonstration: A dynamically adaptable image processing application running in an FPGA-based WSN platform,” 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, 2015, pp. 1902-1902.

2014

• J. Valverde et al., “A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems,” 2014 24th International Conference on Field Programmable Logic and Applications (FPL), Munich, 2014, pp. 1-4.

• A. Rodríguez, J. Valverde, E. de la Torre and T. Riesgo, “Dynamic management of multikernel multithread accelerators using Dynamic Partial Reconfiguration,” 2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), Montpellier, 2014, pp. 1-7.

PhD Theses

2020

• Rodríguez Medina, Alfonso (2020). A Framework to Support Run-Time Adaptation in Reconfigurable Multi-Accelerator Systems. Thesis (Doctoral), E.T.S.I. Industriales (UPM).

2015

• Valverde Alcalá, Juan (2015). Run-Time Dynamically-Adaptable FPGA-Based Architecture for High-Performance Autonomous Distributed Systems. Thesis (Doctoral), E.T.S.I. Industriales (UPM).